1. Field of the Invention
The present invention relates to a cache memory control circuit and a processor, and particularly relates to a cache memory control circuit and a processor for a cache memory having a plurality of ways.
2. Description of the Related Art
Conventionally, in a processor, a cache memory has been generally used for reading or writing data from or to a main memory at a high speed (with low latency). The cache memory is provided between a central processing unit (hereinafter, referred to as “CPU”) and the main memory.
Some cache memories store a plurality of pieces of tag data of the same entry address, that is, have a plurality of ways. Based on an entry address in an address from the CPU, such a cache memory simultaneously reads tags from all the ways, and simultaneously compares the tags with a frame address. When any tag matching (hit) occurs, such a cache memory outputs a word indicated by a word address, in data read from the way which has hit, to the CPU.
In recent years, for example, as disclosed in Japanese Patent Application Laid-Open Publication No. 2002-236616, a cache memory having two access modes in order to save power in the processor has been proposed. According to the proposition, a tag comparison is performed for all the ways in a normal access mode, while a tag comparison is performed only for a selected way in a unique access mode. As a result, in the unique access mode, only a minimum necessary memory area operates, which results in a reduction in power consumption.
However, in the unique access mode in the above described proposition, a cache memory area to be used is limited. Therefore, even if the same software operates, a frequency of cache misses may increase in comparison with the normal access mode. In such a case, since a cache refill operation frequently occurs, power consumption is not sufficiently reduced.
Furthermore, if switching between the access modes is not appropriately performed, the power consumption may also not be sufficiently reduced.